Introduction
  • About the instructor
  • Important Note
  • Motivation to learn Cortex Family of Processors
  • Processor Core Vs Processor
  • Processor Vs Microcontroller
  • Download Source code
Hardware/Software Requirements
  • Hardware/Software Requirements
IDE installation
  • Note for the students
  • About IDE
  • Installing IDE on windows
  • Installing IDE on ubuntu
  • Embedded Target used in this course
  • Documents
Embedded Hello World
  • Note for the students
  • Creating helloworld project
  • Printf using SWV
  • Testing helloworld program on target
  • Printf using semihosting
Access level and operation modes of the processor
  • Features of Cortex Mx Processor
  • Operational Modes of the Cortex Mx Processor
  • Operation modes code demonstration
  • Access level of the processor
  • Core registers part-1
  • Core registers part-2
  • Core registers part-3
  • Memory mapped and non memory mapped registers of the MCU
ARM GCC inline assembly coding
  • ARM GCC inline assembly coding part-1
  • ARM GCC inline assembly coding part-2
  • ARM GCC inline assembly coding part-3
  • ARM GCC inline assembly coding part-4
Reset sequence of the processor
  • Reset sequence of the processor
  • Reset sequence of the processor contd
Access level and T bit
  • Demonstration of access level of the processor
  • Importance of T bit of the EPSR
Memory map and bus interfaces of ARM Cortex Mx processor
  • Memory map
  • Bus protocols and bus interfaces
  • Bit banding
  • Bit band exercise
Stack memory and placement
  • Introduction to stack memory
  • Different stack operation models
  • Stack placement
  • Banked stack pointer registers of ARM Cortex Mx
  • Stack exercise
  • Stack exercise contd.
  • Function call and AAPCS standard
  • Stack activities during interrupt and exception
Exception model of ARM Cortex Mx processor
  • Exception model
  • Different system exceptions
  • system exception vector addresses
  • System exception control registers
  • NVIC
  • NVIC registers
  • Peripheral interrupt exercise
  • Peripheral interrupt exercise contd.
Interrupt priority and configuration
  • Interrupt priority explanation
  • pre-empt and sub priority
  • Interrupt priority configuration exercise
  • Pending interrupt behavior
Exception entry and exit sequences
  • Exception entry and exit sequences
  • Analyzing stack contents during exception entry and exit
Fault handling and analysis
  • Introduction to processor faults
  • Hardfault exception
  • Other configurable faults
  • Configurable fault exception exercise-1
  • Analyzing stack frame
  • Configurable fault exception exercise-2
  • Analyzing stack frame
Exception for system level services
  • SVC exception
  • Extracting SVC number
  • SVC number exercise part-1
  • SVC number exercise part-2
  • SVC math operation exercise
  • PendSV exception
Implementation of task scheduler
  • Introduction
  • Creating user tasks
  • Stack pointer selection
  • Tasks and scheduling
  • Case study of context switching
  • Configure systick timer
  • Case study of context switching contd.
  • Initialization of stack
  • Initialization of stack contd.
  • Stack pointer setup
  • Implementing the systick handler