Introduction
  • Course Structure
  • Instructor Introduction
  • Motivation: Hardware Design
  • Motivation: Let's make a CPU!
  • Motivation: CPU Design
  • Useful Software
Hardware Description Languages
  • What exactly is a Hardware Description Language?
  • Concurrent Design
  • Verilog and VHDL
  • Other HDLs
[Optional] Refresher on Digital Circuit Design
  • Digital Circuit Design
  • Logic Gates
  • Boolean Algebra
  • Combinational Logic - Muxes and Demuxes
  • Combinational Logic - Logic with Multiplexers
  • Combinational Logic - Logic with Demultiplexers
  • Combinational Logic - Inside Multiplexers and Demultiplexers
  • Arithmetic with Gates
  • Adders with Gates
  • Sequential Logic
  • Tri-State Buffers
The Verilog Hardware Description Language
  • Before we start...
  • No, Wait. This is all concurrent!
  • Verilog Code Structure
  • Descriptive Modules
  • Test Bench Modules
  • Some details about Verilog
Software Tutorial
  • EDA Tools
  • Typical Steps in EDA Suites
Quick Overview of EDA Playground
  • Creating a Playground
  • Setting up a Playground
  • Entering Descriptive Code
  • Entering Test Bench Code
  • Entering display System Tasks
  • Simulating with display Tasks
  • Simulating with EPWave
  • Simulating with GTKWave
Quick Overview of Modelsim
  • Download and Installation Tips
  • Compiling
  • Simulation Setup
  • Waveform Simulation
  • More on Timescales
  • More Features
Coding Elements of Verilog
  • Wires and Registers
  • Number Representation: Logic Values
  • Number Representation: Integers
  • Logic Gates
  • The Basics
  • Higher-Level statements
  • Data Assignments
  • Multiplexers and Demultiplexers
  • case statements
  • if-else
  • Hardwired assign
  • Tri-State Buffers in Veriog
  • Tri-State Buffer Implementation in Verilog
  • Sequential Logic
  • Sequential Logic Example in Verilog
  • Blocking vs Nonblocking Assignments
  • Assignment example in EDA Playground
  • Blocking Results
  • Nonblocking Results
  • Nonintuitive Results
A Combinational System Example
  • Let's make a 4-bit Adder!
  • A Verilog Implementation
  • Simulating with Multiple Source Files
  • Simulation
  • Test Bench
  • Propagation Delays
  • An Alternative Implementation in Modelsim
  • Multiple Bit Signals in Modelsim
  • Design an ALU
A Sequential System Example
  • Let's make an Up/Down Counter!
  • A Verilog Implementation
  • Simulation
  • Design a Digital Clock
Wrap Up
  • Think of all the things we learned!
  • What's Next
  • Farewell
  • Verilog Basics Assessment
  • Bonus Lecture: LabsLand and more from Closure Labs!