Introduction
  • Welcome to the Course
  • Background
  • VHDL Usage Example 1 - Circuit Simulation
Objects
  • Objects
  • Signals
  • Signal Example
  • Variables
  • VHDL Variable Example
  • Constants
  • Files
Data Types
  • Standard Logic 1164
  • Standard Logic Text IO Package
  • Standard Logic Arithmetic
  • Numeric Bit
Loops and Statements
  • IF Statement
  • CASE Statement
  • LOOP Statement
  • NEXT Statement
  • EXIT Statement
Design Structure
  • Entity Example 1 - Digital Logic Circuit
  • Entity Example 2 - Multiplexer
  • Architecture Example 1 - Digital Logic Circuit
  • Architecture Example 2 - Multiplexer
Data Flow Design Style
  • Logic Gate VHDL Implementations
  • AND Gate VHDL Design
  • OR Gate VHDL Design
  • Half Adder Data Flow Design
  • Full Adder Dataflow Design
Behavioral Design Style
  • Full Adder Behavioral Design
  • D Flip-Flop Behavioral Design
  • Comparator Behavioral Design
Structural Design Style
  • Full Adder Structural Design
  • Set-Reset Latch Structural Design
  • 2:1 Multiplexer Structural Design
Test Bench Designs
  • Full Adder Test Bench Design
  • D Flip-Flop Test Bench Design
Simulations
  • AND Gate ModelSim Simulation
  • AND Gate Vivado Simulation
  • OR Gate ModelSim Simulation
  • OR Gate Vivado Simulation
  • D-Flip Flop ModelSim Simulation
  • D Flip-Flop Vivado Simulation
  • Full Adder ModelSim Simulation
  • Full Adder Vivado Simulation
FPGA Development Flow Project Using VHDL
  • Priority Encoder VHDL Design
  • Priority Encoder Test Bench Design
  • Priority Encoder Vivado Simulation
  • Priority Encoder IO Assignments
  • Priority Encoder Synthesis and Implementation
  • Priority Encoder Generating Bitstream
  • Program and Configure Your FPGA
  • Test Design on the FPGA
Conclusion
  • Appendix A: Reading VHDL BNF
  • Conclusion