Introduction
  • Welcome to the Course
  • Introduction to the Vivado Tool Suite
  • Vivado Download and Installation
  • Supported FPGAs and Development Boards
Vivado Basics
  • Opening Vivado
  • Creating a New Project in Vivado
  • Importing a Xilinx ISE Project Into Vivado
  • Create a Project From a Predefined Template
  • Vivado Example Project
  • Add Existing Files to a Project
  • Creating New Files
  • Working with Block Designs in Vivado
  • Generating the FPGA Configuration File
  • Programming Your Development Board
  • Documentation Navigator
Pin Planning Tool
  • I/O Pin Planning Tool Introduction
  • Create an I/O Pin Planning Project
  • Create and Place I/O Ports
  • Perform a Design Rules Check
  • Report Simultaneous Switching Noise SSN
  • Generate Contraints File and Top Level HDL File
Intellectual Property (IP) Cores
  • Introduction to IP Cores
  • Using IP Cores
  • Create IP Cores from a Specific Directory
  • Create IP Cores from a Block Design
  • AXI Interface Explained
  • Create an AXI IP Core Peripheral Step 1
  • Creating an AXI IP Core Peripheral - Step 2
  • Create an AXI IP Core Peripheral Step 3
  • Customizing IP Cores
  • Creating a Custom IP Core Repository
  • IP Core Repository Directory Structure
  • Adding IP Cores to Your Repository
  • Adding a Custom IP Core Repository to a Vivado Project
  • Managing a Custom IP Core Repository
IP Core Design Examples
  • Configure Internal FPGA Block RAM (BRAM)
  • Xilinx Memory Interface Generator (MIG) IP Core
  • Connecting Multiple AXI Peripherals to a Single Master
  • Using Vivado's Connection Automation and Regerating Block Design Layouts
Working with Design Constraints
  • What are Design Constraints
  • Applying I/O Constraints
  • Creating Clock Constraints
Automating Vivado
  • TCL Script Introduction
  • Build a Vivado Project Using TCL Scripts
  • Populate a Block Design Using TCL Scripts
  • Using TCL Scripts in Your Custom IP Core
  • How to Create Your Own Custom TCL Scripts
Hardware Design Debugging and Verification
  • Creating Simulation Files (Test Benches)
  • Simulating Your Designs in Vivado
  • Modifying the Simulation Waveform
  • Forcing Signal Values for Simulation
  • Vivado Debugging Tools Introduction
  • How to Use the Integrated Logic Analyzer (ILA) Core for Debugging
  • How to Use the Virtual I/O (VIO) Core for Debugging
Working with Soft Core Processors
  • Creating Your First Softcore Processor Project
  • Add AXI Peripherals to Your MicroBlaze Processor
High Level Synthesis Tool
  • High Level Synthesis Tool Introduction
Programming the FPGA
  • Vivado Hardware Manager Introduction
  • Prior to Programming Checklist
  • Loading the Configuration File on the FPGA
Project Design Flow Example Using Vivado
  • Project Design Flow Walkthrough
  • Step 1 - Acquire Project Requirements
  • Step 2 - Select FPGA Based on Requirements
  • Step 3 - Create Project in Vivado
  • Step 4 - Add Existing / Custom IP
  • Step 5 - Add / Create Design Constraints
  • Step 6 - Simulate and Verify Design
  • Step 7 - Generate the FPGA Configuration File
  • Step 8 – Program your Board to Verify Functionality
Conclusion
  • Conclusion