Welcome and introduction to SystemVerilog Assertions
- Welcome and introduction to SystemVerilog Assertions
- What is an Assertion? What are the benefits? Project wide methodology guidelines
Immediate Assertions
- Types of assertions, Immediate and Deferred immediate assertions
Concurrent Assertions – Basics
- Sequence, Property, Assert and Cover. Implication Operator (Overlapping, Non-ove
- Vacuous PASS
- Clocking basics (singly clocked properties)
- Multi-threading, Formal arguments, disable iff and severity levels
- Binding properties
Concurrent Assertions – Sampled Value Function
- Sampled value Functions (PART 1): $rose, $fell
- Sampled Value Functions (PART 2) : $stable, $past, $changed, $sampled
Concurrent Assertions – Operators
- Clock delay operator
- Consecutive repetition
- Non-consecutive repetition, Non-consecutive GoTo
- ‘throughout’, ‘within’
- ‘and’, ‘or’, ‘intersect’
- 'and', 'or', 'intersect - further nuances
- ‘first_match’, ‘if … else’, ‘iff’, ‘implies’
- first_match : further nuances
System Functions and Tasks
- $onehot, $onehot0, $isunknown, $countones and assertion execution control tasks
Multiply clocked properties and sequences
- Multiply clocked properties and sequences and operators 'and', 'or', etc.
- Multiple Clocks : Further nuances
Local Variables and Endpoint sequence methods
- Local Variables
- Taking care of False Positive using Local Variables
- Modeling variable delay using local variables
- Local variable usage with 'and' and 'or' of sequences
- .triggered, .matched, Calling subroutines, sequence as a formal argument, sequen
Misc IMPORTANT Topics
- ‘expect’, ‘assume’ Blocking ‘action block’
- Asynchronous FIFO Assertions
- Calling subroutines, sequence in sensitivity list and cyclic dependency
- Recursive Property
- Concurrent assertions fired from a procedural block and multiple implications
IEEE-1800: LRM 2009/2012 features
- ‘let’ declarations and ‘checker’
- Checker : Legal and Illegal Conditions
- Strong/weak properties, 'always', 'eventually' and 'followed-by' operators
QUIZZES
- QUIZ 1: Synchronous FIFO assertions
- QUIZ 2: Up-Down Counter
- QUIZ 3: Generic Bus Protocol
- QUIZ 4: PCI Bus Protocol
SystemVerilog Functional Coverage Introduction and Methodology
- Introduction
- SystemVerilog Functional Coverage Methodology
SystemVerilog Functional Coverage Language Features
- 'COVERGROUP' and 'COVERPOINT'
- 'bins'
- 'cross' coverage
- 'cross' further nuances
- 'transition' coverage
- widlcard bins, illegal_bins, ignore_bins, binsof, intersect
- 'bins' filtering
- 'Class' based functional coverage
QUIZ :: Functional Coverage
- QUIZ :: Functional Coverage
Performance implications and coverage methodology
- Performance implications and coverage methodology
- Querying for coverage
- coverage options and examples
